Integration of SHA-2 FPGA implementation with RISC-V core – Mgr. Rajesh Chandrakant Mehta
Mgr. Rajesh Chandrakant Mehta
Master's thesis
Integration of SHA-2 FPGA implementation with RISC-V core
Integration of SHA-2 FPGA implementation with RISC-V core
Abstract:
V moderních dnech je většina vývoje upřednostňována volný, uvolnit open source. V tomto směru akademie zahájila práci zdarma open source instrukční sada architektury (ISA) pro design a rozvoj procesoru. Taková činnost pokračuje na IIT v Chennai pod jménem SHAKTI [1] s podporou od UC, Berkeley. Je založen na technologii RISC V Core. Cílem této práce je integrovat implementace SHA-2 [2] FPGA s SHAKTI …moreAbstract:
In modern days, most of the developments are preferred over free open source. In this direction, academia has initiated the work in free open source Instruction Set Architecture (ISA) for design and development of processor. Such an activity is progressing at IIT, Chennai under the name of SHAKTI [1] with the support from UC, Berkeley. It is based on RISC V Core. The objective of this thesis is to …more
Language used: English
Date on which the thesis was submitted / produced: 14. 12. 2017
Identifier:
https://is.muni.cz/th/hopn0/
Thesis defence
- Date of defence: 1. 2. 2018
- Supervisor: prof. Ing. Václav Přenosil, CSc.
- Reader: Prof. Veezhinathan Kamakoti, Ph.D.
Citation record
Full text of thesis
Contents of on-line thesis archive
Published in Theses:- světu
Other ways of accessing the text
Institution archiving the thesis and making it accessible: Masarykova univerzita, Fakulta informatikyMasaryk University
Faculty of InformaticsMaster programme / field:
Informatics / Information Technology Security (eng.)