Integration of SHA-2 FPGA implementation with RISC-V core

Mgr. Rajesh Chandrakant Mehta

Master's thesis

Abstract:

V moderních dnech je většina vývoje upřednostňována volný, uvolnit open source. V tomto směru akademie zahájila práci zdarma open source instrukční sada architektury (ISA) pro design a rozvoj procesoru. Taková činnost pokračuje na IIT v Chennai pod jménem SHAKTI [1] s podporou od UC, Berkeley. Je založen na technologii RISC V Core. Cílem této práce je integrovat implementace SHA-2 [2] FPGA s SHAKTI jako jedním z nástrojů periferní zařízení ve formátu SoC. Teoretickou část práce je provést rozsáhlý průzkum z literatury [3, 4, 5] pro implementaci SHA-2. Jazyk HDL jako Pro tento účel je použit systém Bluespec System Verilog (BSV) [6] implementace. Po implementaci práce obsahuje i identifikace nejlepší integrační strategie SHA-2 s hostitelem procesor a vyhodnocování toho na základě oblasti, síly a výkon režijní náklady.

Abstract:

In modern days, most of the developments are preferred over free open source. In this direction, academia has initiated the work in free open source Instruction Set Architecture (ISA) for design and development of processor. Such an activity is progressing at IIT, Chennai under the name of SHAKTI [1] with the support from UC, Berkeley. It is based on RISC V Core. The objective of this thesis is to integrate the SHA-2 [2] FPGA implementation with SHAKTI as one of the peripherals in SoC format. The theoretical part of thesis is to carry out extensive survey of the literatures [3, 4, 5] for SHA-2 implementation. HDL language such as Bluespec System Verilog (BSV) [6] is utilized for this implementation. Subsequent to the implementation, thesis includes the identification of best integration strategy of the SHA-2 design with the host processor and evaluation of the same based on area, power and performance overheads.

Keywords

RISC- V Core, Secure Hash Algorithm-2, Bluespec System Verilog, SHAKTI C-64, High Level Synthesis Language, Field Programmable Gate Arrays.

Language used: English

Date on which the thesis was submitted / produced: 14. 12. 2017

Thesis defence

• Date of defence: 1. 2. 2018
• Supervisor: prof. Ing. Václav Přenosil, CSc.
• Reader: Prof. Veezhinathan Kamakoti, Ph.D.

Masaryk University

Faculty of Informatics

Master programme / field:
Informatics / Information Technology Security (eng.)