Hardware - constrained Packet Classification

Mgr. David Antoš, Ph.D.

Doctoral thesis

Abstract:

The goal of this work is to propose a unified packet classification method combining routing, level 3-to-level 2 address translation (ARP), and packet filtering, that can be implemented on a single packet classification unit with a content addressable memory (CAM) and a static RAM. As the target architecture of this work is a general purpose computer equipped with a hardware acceleration card and the operating system being able to classify all the packets even though at lower rate compared to the acceleration card, the packet classification may be partially postponed for the operating system. The ultimate goal is to maximise the amount of traffic confined to the hardware classification unit. The method of combining routing, ARP, and packet filtering into a single lookup operation consists of two separate parts. First, routing and ARP are combined to a single trie-based structure called routing-ARP table that solves both steps at once. We have introduced a formalism for routing and ARP and we have proven correctness of the combined structure. Second, the novel representation of packet filters called Filtering Decision Diagram (FDD) is added. The FDD is a special type of binary decision diagrams with semantical relationship among nodes. Compared to previous decision diagram representations of packet filters, FDDs reflect natural properties of filters and incorporate the concept of encoding rule order directly to the structure. Granularity of a decision node corresponds to a single term of a filtering language, as opposed to binary decision diagram representations where a single bit is the unit of processing (which is not feasible in CAMs). We describe procedures to build FDD representations out of packet filters. Based on the principle of distributing relevant filters to relevant portions of destination address space, the routing-ARP table is combined with FDD representations of filters. We define procedures to rewrite the resulting structure into the target hardware architecture, i.e., first match CAM and comparison instructions that finish the classification. Rewriting the resulting structure into the target architecture gives also a general procedure to convert decision diagrams into first match CAMs. Properties of the target hardware architecture limit the degree of freedom in the method. The method is optimised for memory conservation, adaptable to various target memory sizes and insufficient resources of an actual hardware design. Performance of the resulting structures is experimentally verified using a prototype implementation simulation.

Keywords

routing, packet classification, packet filters, hardware acceleration, CAM

Language used: English

Date on which the thesis was submitted / produced: 22. 9. 2006

Thesis defence

• Date of defence: 12. 10. 2006
• Supervisor: prof. RNDr. Luděk Matyska, CSc.

Masaryk University

Faculty of Informatics

Doctoral programme / field:
Informatics / Informatics