Theses 

Parallelization of brute force attack on MD5 hash algorithm in FPGA – Mgr. Maruthi Gillela

česky | in English | slovensky

Agenda:
Změnit agendu. Adresa v ISu:

Zpět na vyhledávání

Masarykova univerzita

Fakulta informatiky

Magisterský studijní program / obor:
Informatika / Bezpečnost informačních technologií (angl.)

Mgr. Maruthi Gillela

Diplomová práce

Parallelization of brute force attack on MD5 hash algorithm in FPGA

Parallelization of brute force attack on MD5 hash algorithm in FPGA

Anotace: FPGA implementation of MD5 hash algorithm is faster when compared to software implementation, but brute-force attack on MD5 still needs 2^(128) iterations theoretically. This work will explore the possibilities of improving the speed of brute-force attack on FPGA implementation of MD5 algorithm. The student will propose a design/method in FPGA to parallelize the search for a password that was hashed with the MD5 algorithm. The student will then implement the proposed design in an FPGA. As a proof of concept the student will then demonstrate the result for various password lengths suitable to run within reasonable amount of time, and compare performance with the sequential implementation of brute-force attack in an FPGA as well as on a PC.

Abstract: FPGA implementation of MD5 hash algorithm is faster when compared to software implementation, but brute-force attack on MD5 still needs 2^(128) iterations theoretically. This work will explore the possibilities of improving the speed of brute-force attack on FPGA implementation of MD5 algorithm. The student will propose a design/method in FPGA to parallelize the search for a password that was hashed with the MD5 algorithm. The student will then implement the proposed design in an FPGA. As a proof of concept the student will then demonstrate the result for various password lengths suitable to run within reasonable amount of time, and compare performance with the sequential implementation of brute-force attack in an FPGA as well as on a PC.

Keywords: LUT, HDL, GPU, IP core, AXI Bus

Jazyk práce: angličtina

Obhajoba závěrečné práce

  • Obhajoba proběhla 1. 2. 2019
  • Vedoucí: prof. Ing. Václav Přenosil, CSc.
  • Oponent: RNDr. Zdeněk Matěj, Ph.D.

Citační záznam

Citace dle ISO 690: LaTeX | HTML | text | BibTeX | Wikipedie

Plný text práce

Obsah online archivu závěrečné práce
Zveřejněno v Theses:
  • světu
Složka Odkaz na adresář do lokálního úložiště instituce
Jak jinak získat přístup k textu

Instituce archivující a zpřístupňující práci: Masarykova univerzita, Fakulta informatiky


Nahoru | Aktuální datum a čas: 26. 3. 2019 11:39, 13. (lichý) týden

Soukromí

Kontakty: theses(zavináč/atsign)fi(tečka/dot)muni(tečka/dot)cz