Analysis and Design of Metrics for Hardware Trojans

Mgr. Dilip Kumar Dalei

Master's thesis

Abstract:

Integrated Circuit (IC) has become an ubiquitous component of every modern scientific and consumer products. The successful operation of these products depends heavily on internal components, resulting in a huge demand for low-cost chips in the market. As a result, IC industry has re-structured their chip production lifecycle and has started out-sourcing the chip fabrication job to third parties to take benefit of low labour cost. The manufacturing of chips in those untrusted environments raised alarms about reliability and integrity of an IC in industrial applications, especially military and strategic sectors. The illegal modification of chip for malicious purpose cannot be underestimated and hence, it is necessary to devise counter-measures to maintain the trustworthiness of electronic chips. The original circuit of an IC is manipulated intentionally to create disastrous effects in the production systems. The hidden malicious circuit in the original design of a chip is popularly known as the Hardware Trojan (HT). Unlike the Software Trojan, HT poses a major challenge for detection and rectification of the affected chip. Consequently, the chip goes through Trojan detection process and once identified, the chip becomes unusable and gets rejected. Thus it becomes essential for the users to have confidence about the chip integrity based on well-defined metrics. The current project focuses its study on analyzing and modeling such metrics based on internal parameters of the chip. The scope of the work includes a detailed theoretical analysis of parameters and their characterization for Trojan detection. The work also involves the design of a metric, both individual and comprehensive, based on different chip parameters for efficient identification of Trojan. The experiments are conducted using industry-grade EDA tools for synthesis and simulation of Trojan circuits.

Abstract:

Integrated Circuit (IC) has become an ubiquitous component of every modern scientific and consumer products. The successful operation of these products depends heavily on internal components, resulting in a huge demand for low-cost chips in the market. As a result, IC industry has re-structured their chip production lifecycle and has started out-sourcing the chip fabrication job to third parties to take benefit of low labour cost. The manufacturing of chips in those untrusted environments raised alarms about reliability and integrity of an IC in industrial applications, especially military and strategic sectors. The illegal modification of chip for malicious purpose cannot be underestimated and hence, it is necessary to devise counter-measures to maintain the trustworthiness of electronic chips. The original circuit of an IC is manipulated intentionally to create disastrous effects in the production systems. The hidden malicious circuit in the original design of a chip is popularly known as the Hardware Trojan (HT). Unlike the Software Trojan, HT poses a major challenge for detection and rectification of the affected chip. Consequently, the chip goes through Trojan detection process and once identified, the chip becomes unusable and gets rejected. Thus it becomes essential for the users to have confidence about the chip integrity based on well-defined metrics. The current project focuses its study on analyzing and modeling such metrics based on internal parameters of the chip. The scope of the work includes a detailed theoretical analysis of parameters and their characterization for Trojan detection. The work also involves the design of a metric, both individual and comprehensive, based on different chip parameters for efficient identification of Trojan. The experiments are conducted using industry-grade EDA tools for synthesis and simulation of Trojan circuits.

Keywords

Hardware Trojan, Trojan Detection, Trusted IC, Trojan Detection Metric, Static Power, Dynamic Power, Path Delay, Side-channel Parameter, Chip Area, AES-Trojan

Language used: English

Date on which the thesis was submitted / produced: 5. 1. 2017

Thesis defence

• Date of defence: 10. 2. 2017
• Supervisor: prof. RNDr. Václav Matyáš, M.Sc.
• Reader: RNDr. Petr Švenda, Ph.D.

Masaryk University

Faculty of Informatics

Master programme / field:
Informatics / Information Technology Security (eng.)