Designing Optimized Architecture for Solving Elliptic Curve Discrete Log Problem Using Pollard's rho method

Mgr. Harshit Kumar Singh

Master's thesis

Abstract:

Elliptic Curve Cryptography (ECC) is a popular approach used in construction of public-key crypto-systems. The security of ECC is based on the difficulty of solving the Elliptic Curve Discrete Logarithm Problem (ECDLP). Implementing and analyzing the performance of the best known methods to solve the ECDLP can be useful in assessment of security of ECC and selection of security parameters in practice. Scalar multiplication operation uses a field multiplier for both doubling and addition operations, thereby, any improvement in speed of computation of field multiplier will speed up the entire multiplication process. Digital Signal Processing (DSP) blocks have the capability to perform integer multiplication and hence are ideal candidates for application in field multipliers. This work explores a hardware architecture implementing the parallel version of Pollard’s Rho algorithm with Negation Map and fruitless cycle detection to solve the ECDLP. Additionally, the work investigates as to how use of DSP blocks can be minimized to accelerate Elliptic Curve scalar multiplication in prime fields. The thesis explores an asymmetric multiplier design to perform modular multiplication for optimization of DSP blocks configuration and latency. Hardware Description Language (HDL) Bluespec System Verilog (BSV) has been used as the language for implementing the design.

Abstract:

Elliptic Curve Cryptography (ECC) is a popular approach used in construction of public-key crypto-systems. The security of ECC is based on the difficulty of solving the Elliptic Curve Discrete Logarithm Problem (ECDLP). Implementing and analyzing the performance of the best known methods to solve the ECDLP can be useful in assessment of security of ECC and selection of security parameters in practice. Scalar multiplication operation uses a field multiplier for both doubling and addition operations, thereby, any improvement in speed of computation of field multiplier will speed up the entire multiplication process. Digital Signal Processing (DSP) blocks have the capability to perform integer multiplication and hence are ideal candidates for application in field multipliers. This work explores a hardware architecture implementing the parallel version of Pollard’s Rho algorithm with Negation Map and fruitless cycle detection to solve the ECDLP. Additionally, the work investigates as to how use of DSP blocks can be minimized to accelerate Elliptic Curve scalar multiplication in prime fields. The thesis explores an asymmetric multiplier design to perform modular multiplication for optimization of DSP blocks configuration and latency. Hardware Description Language (HDL) Bluespec System Verilog (BSV) has been used as the language for implementing the design.

Keywords

Elliptic Curve Cryptography (ECC), Elliptic Curve Discrete Log Problem (ECDLP), Pollard Rho, Digital Signal Processing (DSP) Blocks, Hardware Description Language (HDL), Bluespec System Verilog (BSV)

Language used: English

Date on which the thesis was submitted / produced: 22. 5. 2017

Thesis defence

• Date of defence: 20. 6. 2017
• Supervisor: prof. RNDr. Václav Matyáš, M.Sc.
• Reader: Mgr. Marek Sýs, Ph.D.

Masaryk University

Faculty of Informatics

Master programme / field:
Informatics / Information Technology Security (eng.)