The CRC code generator for large data blocks

Mgr. Nidhi Pokhriyal

Master's thesis

Abstract:

Cyclic redundancy check(CRC) codes are one of the most frequently used methods for error detection in digital data communication and storage. Short CRC codes are effective when they have to be calculated for small data blocks. However, with an increase in the size of the input data block, the effectiveness of these short CRC codes in error detection does not remain the same and collisions may occur with higher probabilities. Hence for larger data blocks even wider CRC codes are needed to increase the efficacy of CRCs in error detection. This thesis presents the design and implementation of the CRC-256 code generator to increase the effectiveness of CRC codes in error detection for large input data blocks. The designed CRC-256 code generator is implemented in two versions in the field programmable gate array(FPGA). The first version of the generator is designed using linear feedback shift registers. As the second version, an accelerated CRC-256 generator is designed using Slice-by-32 [1] acceleration technique for CRC generation. The implementation of both the CRC-256 generators was carried out in Verilog hardware description language. These Verilog designs of generators were synthesized on various FPGA platforms and evaluated for their power consumption, area requirement, delay and performance.

Abstract:

Cyclic redundancy check(CRC) codes are one of the most frequently used methods for error detection in digital data communication and storage. Short CRC codes are effective when they have to be calculated for small data blocks. However, with an increase in the size of the input data block, the effectiveness of these short CRC codes in error detection does not remain the same and collisions may occur with higher probabilities. Hence for larger data blocks even wider CRC codes are needed to increase the efficacy of CRCs in error detection. This thesis presents the design and implementation of the CRC-256 code generator to increase the effectiveness of CRC codes in error detection for large input data blocks. The designed CRC-256 code generator is implemented in two versions in the field programmable gate array(FPGA). The first version of the generator is designed using linear feedback shift registers. As the second version, an accelerated CRC-256 generator is designed using Slice-by-32 [1] acceleration technique for CRC generation. The implementation of both the CRC-256 generators was carried out in Verilog hardware description language. These Verilog designs of generators were synthesized on various FPGA platforms and evaluated for their power consumption, area requirement, delay and performance.

Keywords

Cyclic redundancy check(CRC), Field programmable gate arrays(FPGA), Look-up table(LUT), Linear feedback shift register(LFSR), Slice-by-N, Verilog, Galois field-2(GF-2).

Language used: English

Date on which the thesis was submitted / produced: 13. 12. 2018

Thesis defence

• Date of defence: 1. 2. 2019
• Supervisor: prof. Ing. Václav Přenosil, CSc.
• Reader: RNDr. Zdeněk Matěj, Ph.D.

Masaryk University

Faculty of Informatics

Master programme / field:
Informatics / Information Technology Security (eng.)