Komunikační reflektor s hardwarovou akcelerací

Bc. Šimon Řeřucha, Ph.D.

Master's thesis

Hardware accelerated communication reflector

Abstract:

The goal of this thesis is to find a way how to improve the performance of the communication mirror (referred to as the packet reflector) which operates on a common computer equipment. As the computer networks become faster and faster the hardware architecture become the bottleneck that limits the performance of network applications operated on the hardware. It is desired to mitigate the impact of this limitation by using a hardware acceleration card being able to duplicate a part of the functionality of reflector. The ultimate goal is to maximize the amount of traffic which the reflector can process. The work of the hardware accelerator is determined by the control information that have to be provided by a support software. As these control information are a "snapshot" of the current configuration of the reflector and the operating system, they have to be maintained continuously in order to reflect the changes in the configuration. We have proposed a consecution to generate the control information which ensures that the accelerator can resend the packet instead of the reflector. This consecution comprises an algorithm to generate currently valid control information and specifies under which circumstances this algorithm must be triggered to obtain a new ones. Moreover, we have proposed some changes of reflector necessary to preserve the behaviour of the accelerated reflector from the external point of view. According to the proposals presented in this thesis we have implemented the changes of the reflector and the algorithm to create the control information. We have developed a simulator of the hardware accelerator using which the implementation has been experimentally verified. Finally, some issues and topics that are subject of further research has been identified and described.

Keywords

UDP packet reflector, Hardware acceleration, HW accelerator Combo, FPGA, Group communication, Hi-speed computer networks

Language used: Czech

Date on which the thesis was submitted / produced: 19. 5. 2006

Thesis defence

• Date of defence: 27. 6. 2006
• Supervisor: doc. RNDr. Eva Hladká, Ph.D.

Masaryk University

Faculty of Informatics

Master programme / field:
Applied Informatics / Applied Informatics